模块基本概念

模块描述形式

逻辑行为描述：

// 二选一多路选择器
module muxtwo(out, a, b, s1);
    input a, b, s1;
    output out;
    reg out;
    always @ (s1 or a or b)
        if (!s1) out = a;
        else out = b;
endmodule

布尔表达式表述：

module muxtwo(out, a, b, s1);
    input a, b, s1;
    output out;
    wire ns1, sela, selb;
    assign ns1 = ~ns1;
    assign sela = a & ns1;
    assign selb = b & s1;
    assign out = sela | selb;
endmodule

逻辑单元互联结构表述：

module muxtwo(out, a, b, s1);
    input a, b, s1;
    output out;
    not u1(ns1, s1);
    and #1 u2(sela, a, ns1);
    and #1 u3(selb, b, s1);
    or #1 u4(out, sela, selb);
endmodule

语法特性

特性：并行性，层次结构性，可综合性

// 3位加法器
module adder(cout, sum, a, b, cin);
    input [2:0] a, b;
    input cin;
    output cout;
    output [2:0] sum;
    assign {cout, sum} = a + b + cin;
endmodule

// 比较器
module compare(equal, a, b);
    output equal;
    input [1:0] a, b;
    assign equal = (a == b) ? 1 : 0; /*多行注释*/
endmodule

// 三态门选择器
module trist2(out, in, enable);
    output out;
    input in, enable;
    bufif1 mybuf(out, in, enable);
endmodule

module trist1(sout, sin, ena);
    output sout;
    input sin, ena;
    mytri tri_inst(.out(sout), .in(sin), .enable(ena));
endmodule

module mytri(out, in, enable);
    output out;
    input in, enable;
    assign out = enable ? in : 'bz;
endmodule

模块测试

`include "muxtwo.v"
module t;
    reg ain, bin, select;
    reg clock;
    wire outw;
    initial begin
        ain = 0;
        bin = 0;
        select = 0;
        clock = 0;
    end
    always #50 clock = ~clock;
    always @ (posedge clock) begin
        #1 ain = {$random} % 2;
        #3 bin = {$random} % 2;
    end
    always #10000 select = !select;
    muxtwo m(.out(outw), .a(ain), .b(bin), .s1(select));
endmodule